With the trend toward higher functions of digital image processing apparatuses, and a higher image quality including a higher resolution, a need has been increased for transferring a large amount of data at high speeds among digital circuits, for example, among LSI'S mounted in a digital image processing apparatus.
FIG. 1 is a block diagram illustrating the configuration of a digital image processing apparatus of a first conventional example including a plasma panel display. Referring to FIG. 1, the digital image processing apparatus comprises an image processing LSI 501, bus lines 502, a driver 503, and a plasma display panel 504. The image processing LSI 501 performs signal processing such as color space conversion, γ-correction and the like, and the resulting image data is transferred to the driver 503 through the bus lines 502 for display on the plasma display panel 504.
Assume herein that each of the upper and lower halves of a plasma display panel having a resolution WXGA (abbreviation of Wide-XGA, meaning the number of pixels of 4095 pixels×768 lines) is driven by a 256-bit, 4-port driver. In this event, an image processing LSI requires a number of output terminals corresponding to 128 (4095 pixels/256 pixels×4 ports×2 areas) bus lines. In other words, in a conventional data transfer method using bus lines for handing binary voltage data, a large number of lines and input/output terminals of LSI's are required, so that a higher cost is anticipated for high-resolution apparatuses which will make their appearance in the future.
The challenge associated with binary voltage data based data transfer which requires a large number of lines and input/output terminals of LSI's can be solved by using a multi-value voltage data rather than the binary voltage data. For example, if 2-bit, 3-bit, or 4-bit binary voltage data is encoded to four-value, eight-value, or 16-value multi-value voltage data and transmitted from the transmission side, and the multi-value voltage data can be restored to the original 2-bit, 3-bit, and 4-bit binary voltage data on the reception side, the foregoing challenge can be solved. In this event, the number of lines can be reduced to ½, ⅓, or ¼ as many as that for a binary voltage data transfer.
However, for performing higher-order voltage multi-value encoding, a voltage per step of each value is reduced due to limitations in supply voltage, causing a relative increase in noise voltage. This makes it difficult to discriminate multiple values on the reception side. For example, when 4-bit binary voltage data is converted to 16-value voltage data which is transferred through a single line, a supply voltage of 3.3 V provides approximately 200 mV of voltage per step. Thus, for a normal data transfer, a noise voltage must be suppressed to one step or less, and the reception side must have a resolution of approximately 200 mV. Generally, high-order multiple value encoding of voltage data is difficult from viewpoints of noise margin and resolution.
For solving the challenge of a data transfer through the multi-value voltage data, there has been provided a data transfer method using multi-value current data. Multi-value current data encoding is suitable for higher value encoding because of a wide noise margin, as compared with multi-value voltage data encoding. For example, Japanese Patent Kokai No. 2001-156621 proposes a data transmission system (second conventional example). FIG. 2 shows this data transmission system. Referring to FIG. 2, binary voltage data output from an internal circuit 601 on the transmission side is converted to multi-value voltage data by a DA converter (DAC: Digital to Analog Converter) 602. The multi-value voltage data is converted to multi-value current data by a PMOS transistor 603. The multi-value current data is transmitted through a single data line 604. On the reception side, the multi-value current data is received by a current mirror circuit 605, and restored to the original binary voltage data by an AD converter (ADC: Analog to Digital Converter) 606. The restored binary voltage data is used in an internal circuit 607. This method can accomplish a data transfer which is less susceptible to the influence of noise between transmission and reception than a multi-value voltage data based data transfer, with a reduced number of bus lines.
However, when the second conventional example is applied to a digital image processing apparatus, following problems arise. After binary voltage data is converted to a multi-value voltage data by the DA converter 602, the multi-value voltage data is converted to multi-value current data by the PMOS transistor 603. Therefore, the voltage data is still susceptible to the influence of noise on the transmission side.
Also, when high-order multi-value encoding is performed on the transmission side, the DA converter 602 requires a large amount of hardware. In addition, since a sequential comparison type AD converter 606 is employed, the value is established from the most significant bit in order in the conversion from multi-value current data to binary-value voltage data. Thus, a long time is required on the reception side in order to restore original binary voltage data from multi-value current data.
What is desired is a data transfer method and circuit which are less susceptible to the influence of noise on the transmission side, require a small amount of hardware for conversion from binary voltage data to multi-value current data, and restore original binary voltage data from the multi-value current data at high speeds on the reception side.
Patent Document: Japanese Patent Kokai No. 2001-156621